Designing Testability Into An Existing Microprocessor Board

dc.contributor.authorPaulson, Michael C.
dc.date.accessioned2022-06-17T21:54:12Z
dc.date.available2022-06-17T21:54:12Z
dc.date.issued1992
dc.date.published1992
dc.description.abstractThis thesis presents the hardware implementation of a microprocessor system built according to the microprocessor-controlled Built-In Self-Test (BIST) techniques as presented by Gordon [Gordon 1991 a]. It covers issues relating to the isolation of the edge connector and secondary board areas, to the use and function of a fieldprogrammable gate array (Logic Cell Array)n", to the implementation of electronic wraparounds, and to the general design of the software to support the testability features. In addition, it covers the general use of the ANSI/IEEE Std. 1149.1 test bus for diagnosis, isolation, and board-level partitioning.
dc.description.degreeMaster of Science
dc.description.departmentDepartment of Electrical and Computer Engineering
dc.description.levelMasters
dc.identifier.urihttps://hdl.handle.net/2097/42329
dc.language.isoen_US
dc.publisherKansas State Universityen
dc.publisherKansas State University
dc.rightsThis Item is protected by copyright and/or related rights. You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s).
dc.rights.urihttps://rightsstatements.org/vocab/InC/1.0/
dc.titleDesigning Testability Into An Existing Microprocessor Board
dc.typeThesis

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