Designing Testability Into An Existing Microprocessor Board

Abstract

This thesis presents the hardware implementation of a microprocessor system built according to the microprocessor-controlled Built-In Self-Test (BIST) techniques as presented by Gordon [Gordon 1991 a]. It covers issues relating to the isolation of the edge connector and secondary board areas, to the use and function of a fieldprogrammable gate array (Logic Cell Array)n", to the implementation of electronic wraparounds, and to the general design of the software to support the testability features. In addition, it covers the general use of the ANSI/IEEE Std. 1149.1 test bus for diagnosis, isolation, and board-level partitioning.