The future of semiconductor manufacturing: EUV lithography

Abstract

The global semiconductor industry is projected to grow exponentially from $775 billion to $1.6 trillion by 2030 which has motivated companies to find more efficient ways to manufacture semiconductors by reducing costs or reducing transistor sizes as proposed by Moore’s Law. Once DUV lithography hit its cap at 32 nm node sizes with immersion lithography, a new lithographic technique needed to be developed in order to continue the shrinkage; EUV lithography, first readily used, in 2019, provided an innovative way to push node sizes to sub-7 nm by decreasing the wavelength of light by 14x. With the adoption of EUV lithography in advanced logic and memory-based applications, there still continues to be innovation aimed at increasing overall process efficiency through process improvements, as well as pushing node sizes even smaller to most recently <2nm with the introduction of the next generation EUV technology. This report provides a deep understanding of the EUV process that is critical for maintaining the pace of transistor miniaturization. In order to accomplish this, everything relating to the EUV process: fundamentals, system architecture, masks and pellicles, photoresists, technical challenges, industrial adoption, recent advances, and future possibilities are explained. Despite ongoing challenges, recent advancements in this space have spurred next generation lithographic techniques along with the potential to make EUV lithography realistic for more mature nodes.