ELID grinding of silicon wafers: a literature review

dc.citation.doi10.1016/j.ijmachtools.2006.06.001
dc.citation.epage536en_US
dc.citation.issue3-4en_US
dc.citation.jtitleInternational Journal of Machine Tools and Manufactureen_US
dc.citation.spage529en_US
dc.citation.volume47en_US
dc.contributor.authorLiu, J. H.
dc.contributor.authorPei, Zhijian J.
dc.contributor.authorFisher, Graham R.
dc.contributor.authoreidzpeien_US
dc.date.accessioned2009-11-25T22:13:07Z
dc.date.available2009-11-25T22:13:07Z
dc.date.issued2007-03-01
dc.date.published2007en_US
dc.description.abstractSilicon wafers are the most widely used substrates for fabricating integrated circuits. There have been continuous demands for higher quality silicon wafers with lower prices, and it becomes more and more difficult to meet these demands using current manufacturing processes. In recent years, research has been done on electrolytic in-process dressing (ELID) grinding of silicon wafers to explore its potential to become a viable manufacturing process. This paper reviews the literature on ELID grinding, covering its set-ups, wheel dressing mechanism, and experimental results. It also discusses the technical barriers that have to be overcome before ELID grinding can be used in manufacturing.en_US
dc.description.versionArticle: Accepted Manuscript
dc.identifier.urihttp://hdl.handle.net/2097/2192
dc.relation.urihttps://doi.org/10.1016/j.ijmachtools.2006.06.001en_US
dc.rightsThis Item is protected by copyright and/or related rights. You are free to use this Item in any way that is permitted by the copyright and related rights legislation that applies to your use. For other uses you need to obtain permission from the rights-holder(s).
dc.rights.urihttps://rightsstatements.org/page/InC/1.0/
dc.subjectElectrolytic in-process dressingen_US
dc.subjectGrindingen_US
dc.subjectMachiningen_US
dc.subjectSemiconductor materialen_US
dc.subjectSilicon waferen_US
dc.titleELID grinding of silicon wafers: a literature reviewen_US
dc.typeTexten_US

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