Corrective schemes for internal and external abnormalities in cascaded multilevel inverters

Abstract

Corrective schemes for facilitating continued operation of dc-ac converters during internal and external abnormalities are presented in this dissertation. While some of the developed techniques are suited for any dc-ac converter topology, most of the presented methodologies are designed specifically for cascaded H-bridge (CHB) multilevel converters. While CHB provide increased scalability and efficiency compared to traditional topologies, these converters are more likely to experience internal faults due to the additional components required. Realizing the full potential of CHB converters requires fault tolerant techniques, such as those demonstrated in this dissertation. Adaptive sinusoidal pulse width modulation (ASPWM) is introduced in this dissertation as a method which enables CHB to directly utilize time-variant dc sources, increasing CHB flexibility when compared to traditional pulse width modulation (PWM) methods which require dc sources with equal magnitudes or with magnitudes existing in specific ratios. Two alternative algorithms are presented to enable ASPWM implementation, providing a trade off between system performance and required sensor circuitry. This dissertation also introduces a load independent analytical approach for identifying discordant operating points, i.e. operating points where some cells in an asymmetric CHB leg regenerate power while the overall leg delivers power, or vice-versa. Identification of these points is essential due to the deleterious effects which can result from extended discordant operation, for instance overcharging of batteries leading to lifespan degradation or even catastrophic failures such as fires or explosions. Additionally, a method for rapidly identifying, isolating, and verifying internal IGBT open-circuit and gate-driver faults is presented in this dissertation to address the increased probability of switch failures occurring within CHB. The proposed approach enables converter operation to continue in the event of gate-driver or open-circuit faults, but avoids unnecessary converter reconfiguration due to gate-misfiring faults. For a CHB leg with M cells, the proposed technique identifies and isolates open-circuit switch faults in less than 2M measurement (sampling) cycles, and verification is completed in less than one full fundamental cycle. Furthermore, this dissertation introduces a real-time implementable atypical PWM technique which enables increased dc bus utilization under a wide range of non-ideal operating conditions. While this approach is suitable for a wide range of converters operating under external abnormalities, for instance maximizing dc bus utilization for converters providing auxiliary services such as negative-sequence compensation, this approach also facilitates operation of CHB with faulty cells. The proposed method can be used with any control technique and any carrier-based PWM method, enabling its implementation in both symmetric and asymmetric CHB. In addition to these fault tolerant techniques, a novel approach for analyzing the active- and reactive-power deliverable by grid-interactive converters is proposed. This method facilitates performance comparisons for various converter configurations, simplifying the process for selecting filter components, dc bus voltages, and other system parameters. This analytical approach also enables converter performance to be analyzed during internal and external fault events, allowing assessment of converter robustness. The efficacy of the developed techniques are supported by MATLAB/Simulink simulations as well as experimental data obtained using a laboratory-scale cascaded H-bridge multilevel converter.