Low-power packet synchronization scheme implemented on field programmable gate array - Carlson, Charles (Kansas State University, 2015)
Synchronization is one of the most critical steps in a wireless communication system. With the system having limited energy resources, low power devices and designs are key aspects of the design process. Digital communication and decoding is discussed along with how synchronization is part of communication. The parameters for wireless communication are outlined and how the system can be simplified in order to reduce power consumption for the network is investigated. The background for the Body Area Network Board which was created for the project, Biosensor Networks and Telecommunication Subsystems for Long Duration Missions, EVA Suits, and Robotic Precursor Scout Missions, is discussed along with some synchronization background as well as some previously researched demodulators designed for limited preambles. With limited-length preambles, oversampling is needed to achieve synchronization. This research investigates what minimum oversampling ratio is needed in a simplified system to still achieve packet synchronization and several synchronization words were compared. The parameters for packet synchronization are outlined as well the impulse noise model used for simulation. For the simulation and the test setup, several oversampling ratios and synchronization words are compared using probability of miss detection and probability of false detection. The oversampling ratio of 16 was shown to be a critical point where increasing the oversampling rate above 16 had diminishing returns. In terms of probability of miss detection, the 7-bit Barker sequence along with the start of frame delimiter for IEEE 802.15.4 had better performance compared to the start of frame delimiter for Ethernet and the sequence 01010111.
Keywords: Low power; Packet synchronization; FPGA; Electrical Engineering (0544)