Toward optimality in power-efficient low-noise amplifier design - Lindstrom, Bo E. (My University, 2026)
Power-efficient Low Noise Amplifier design poses numerous challenges. Often power is down-scaled at the expense of other amplifier performance metrics such as gain, linearity, noise figure, etc. This document proposes solutions to ease the trade-off between power and performance. Namely, a design methodology is described which moves the state-of-the-art in low-power LNAs closer to a Pareto Optimal Voltage Distribution. This approach seeks to carefully choose voltage and current distributions in each FET at every gain-stage to maximize performance, and achieves this end through the stacking of transistors between the supply and ground. This technique was realized in a device that is referred to as the 'C/X-band LNA', which is fabricated in a 45nm silicon-on-insulator (SOI) process. S-Parameter measurements show a peak voltage gain of 24.1dB, a bandwidth of 2.9GHz, and a center frequency of 8GHz. The measured noise figure of the C/X-band LNA is found to be 4.5dB. Furthermore, a reconfigurable LNA (also fabricated in 45nm SOI), extends the Pareto Optimal Voltage Distribution design philosophy to a reconfigurable LNA whose bandwidth is tuned through judicious use of capacitor digital-to-analog converters (DACs). This results in a device which pushes the limits of the state-of-the-art from a performance standpoint, while showing a high degree of tolerance to jammers and blockers. In addition to reconfigurability, the amplifier also shows superior noise and voltage gain in all measured states when compared to the C/X-band LNA. Finally, a Ku-band LNA is proposed and rigorously simulated. Designed in the same 45nm node as Amplifier 1 and Amplifier 2, it seeks to optimize linearity. The 1dB compression point is extended in the amplifier’s output stage through the use of a dynamic bias circuit. IP2 is effectively cancelled through the use of a complementary cascode structure at the output. IP3 is nulled by leveraging derivative superposition, also at the output. The proposed amplifier's simulated noise figure is also superior to both the C/X-band LNA and the reconfigurable LNA, as simultaneous noise and impedance matching is achieved at the single-ended input stage. This research drives the state-of-the-art forward by moving towards a Pareto Optimal Voltage Distribution, which allows for marked power savings in LNAs at minimal cost to gain, noise, and linearity. Additionally, a highly robust anti-jammer/blocker technique is integrated with a Pareto Optimal design demonstrating its far-reaching applicability to niche design concerns. Finally, an amplifier with a highly linear output stage is proposed which effectively optimized 1dB compression point, while also nulling second and third order non-linearities. All of these designs are proposed and/or fabricated in a 45nm SOI process, and are among the leaders in aggregate performance when compared to recently published low-power LNA designs.
Keywords: CMOS; Low-noise amplifier; Integrated circuit design; Radio frequency; Low-power electronics