The effects of hardware acceleration on power usage in basic high-performance computing
dc.contributor.author | Amsler, Christopher | |
dc.date.accessioned | 2012-04-30T14:49:56Z | |
dc.date.available | 2012-04-30T14:49:56Z | |
dc.date.graduationmonth | May | en_US |
dc.date.issued | 2012-04-30 | |
dc.date.published | 2012 | en_US |
dc.description.abstract | Power consumption has become a large concern in many systems including portable electronics and supercomputers. Creating efficient hardware that can do more computation with less power is highly desirable. This project proposes a possible avenue to complete this goal by hardware accelerating a conjugate gradient solve using a Field Programmable Gate Array (FPGA). This method uses three basic operations frequently: dot product, weighted vector addition, and sparse matrix vector multiply. Each operation was accelerated on the FPGA. A power monitor was also implemented to measure the power consumption of the FPGA during each operation with several different implementations. Results showed that a decrease in time can be achieved with the dot product being hardware accelerated in relation to a software only approach. However, the more memory intensive operations were slowed using the current architecture for hardware acceleration. | en_US |
dc.description.advisor | Dwight D. Day | en_US |
dc.description.degree | Master of Science | en_US |
dc.description.department | Department of Electrical Engineering | en_US |
dc.description.level | Masters | en_US |
dc.description.sponsorship | Sandia National Laboratories | en_US |
dc.identifier.uri | http://hdl.handle.net/2097/13742 | |
dc.language.iso | en_US | en_US |
dc.publisher | Kansas State University | en |
dc.subject | Field programmable gate array | en_US |
dc.subject | Power | en_US |
dc.subject | High performance computing | en_US |
dc.subject | Hardware acceleration | en_US |
dc.subject.umi | Computer Engineering (0464) | en_US |
dc.subject.umi | Electrical Engineering (0544) | en_US |
dc.title | The effects of hardware acceleration on power usage in basic high-performance computing | en_US |
dc.type | Thesis | en_US |