Digitally programmable delays for use in a beamforming IC receiver module

Abstract

Phase alignment in beamforming systems is vital for high-performance operation. Phase alignment can be achieved through phase shifts in RF that are produced with the aid of a variable time reference to a frequency synthesizer. In addition, programmable delays are often used to vary the delay of a signal. Programmable delays for linear, high resolution, and wide delay range need to be designed as a single circuit on-chip solution for ICs. Otherwise, parasitic and other effects degrade the performance of the programmable delay. This thesis proposes two possible programmable delays produced using two different tool sets: 1) Cadence Virtuoso, and 2) the combination of Cadence Genus and Cadence Innovus. Additionally, the two proposed programmable delays were designed using different types of MOSFETs: body contact MOSFETs (bulk-MOSFETs) and floating body MOSFETs (SOI-MOSFETS). The floating body MOSFET design suffers from delay step timing stability due to history effect. Programmable delays are characterized by LSB resolution, delay range, differential non-linearity, and integral non-linearity. The programmable delay design using Cadence Virtuoso had an LSB resolution in simulation of 3.24 ps and a total delay range of 6.873 ns with 2119 steps. The other programmable delay design had a simulated LSB resolution of 7.54 ps and a total delay range of 7.72 ns with 1023 steps.