Study of high dielectric constant oxides on GaN for metal oxide semiconductor devices

Abstract

Gallium nitride is a promising semiconductor for fabricating field effect transistors for power electronics because of its unique physical properties of wide energy band gap, high electron saturation velocity, high breakdown field and high thermal conductivity. However, these devices are extremely sensitive to the gate leakage current which reduces the breakdown voltage and the power-added efficiency and increases the noise figures. To solve this problem, employing a gate dielectric is crucial to the fabrication of metal insulator semiconductor high electron mobility transistors (MISHEMTs), to reduce the leakage current and increase the magnitude of voltage swings possible. For this device to be successful, imperfections at the oxide-semiconductor interface must be suppressed to maintain the high electron mobility of the device. This research explored multiple high dielectric constant gate oxides (Al[subscript]2O[subscript]3, TiO[subscript]2, and Ga[subscript]2O[subscript]3), deposited on different crystalline orientations and polarities of GaN by atomic layer deposition (ALD) to form metal oxide semiconductor capacitors, including effects of pretreatment on N-polar GaN, ALD TiO[subscript]2/Al[subscript]2O[subscript]3 nano-laminate on thermal oxidized Ga-polar GaN and ALD Al[subscript]2O[subscript]3 on [Italic]c- and [Italic]m-plane GaN Surface pretreatments were shown to greatly alter the morphology of reactive N-polar GaN which is detrimental to the electrical properties. 14 nm thick ALD Al[subscript]2O[subscript]3 films were directly deposited on N-polar GaN without thermal or chemical pretreatments which yield a smooth surface (RMS=0.23 nm), low leakage current (2.09 x 10[superscript]-[superscript]8 A/cm[superscript]2) and good Al[subscript]2O[subscript]3/GaN interface quality, as indicated by the low electron trap density (2.47 x 10[superscript]10 cm[superscript]-[superscript]2eV[superscript]-[superscript]1). In the nano-laminate study, a high dielectric constant of 12.5 was achieved by integrating a TiO[subscript]2/Al[subscript]2O[subscript]3/Ga[subscript]2O[subscript]3 oxide stack layer, while maintaining a low interface trap density and low leakage current. There was a strong correlation between the surface morphology and electrical properties of the device discovered from comparing the ALD Al[subscript]2O[subscript]3 on [Italic]c- and [Italic]m-plane GaN, namely smooth surface lead to small hysteresis. These results indicate the promising potential of incorporation gate dielectric for future GaN devices.