Reducing phase noise and spurious tones in fractional-n synthesizers

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dc.contributor.author Allegre, Daniel
dc.date.accessioned 2009-08-19T13:01:18Z
dc.date.available 2009-08-19T13:01:18Z
dc.date.issued 2009-08-19T13:01:18Z
dc.identifier.uri http://hdl.handle.net/2097/1684
dc.description.abstract A frequency synthesizer is a control system which employs a reference signal from a component, such as a crystal oscillator, with excellent phase and frequency stability to synthesize higher frequencies with similarly desirable characteristics. Such a control system is at the heart of many communication schemes. Due to the digital circuitry used in frequency synthesis, it is relatively straightforward to synthesize frequencies at integer multiples of the reference signal frequency. A synthesizer which achieves this is called an integer-N frequency synthesizer. The main challenge in the design of integer-N synthesizers is to reduce phase noise introduced by circuitry while achieving a needed frequency resolution. Noise can be spectrally spread by conversions in the loop which are non-linear, so the strategy to reduce noise is two-fold. Control-loop and circuit design techniques can be used to reduce device noise, but it is also important to make sure that the noise performance is not degraded by spectral spreading within the loop. This thesis addresses primarily the latter approach with the design and implementation of circuits targeting a specific conversion within the loop. Frequency resolution of a synthesizer can be improved by introducing additional circuitry and complexity. This additional complexity makes it possible to multiply the reference frequency by a fractional number and thus achieve higher frequency resolution. A control system which achieves this is called a fractional-N frequency synthesizer. The cost associated with the increased frequency resolution is a form of noise that is deterministic called spurious noise. This spurious noise can also be spread and amplified by non-linear conversions in the control loop. A quantitative understanding of the magnitude of this noise that is not readily available in the literature was developed in this research. A comparison between several implementations of integrated frequency synthesis was also carried out in this research with the intent of providing guidelines to produce a better performing synthesizer. These implementations differ in key components of the loop where linearity is of particular importance. en
dc.description.sponsorship Sandia; Honeywell en
dc.language.iso en_US en
dc.publisher Kansas State University en
dc.subject synthesizer en
dc.title Reducing phase noise and spurious tones in fractional-n synthesizers en
dc.type Thesis en
dc.description.degree Master of Science en
dc.description.level Masters en
dc.description.department Department of Electrical and Computer Engineering en
dc.description.advisor William B. Kuhn en
dc.subject.umi Engineering, Electronics and Electrical (0544) en
dc.date.published 2009 en
dc.date.graduationmonth August en


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