A device for synchronous Ethernet packet delay

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dc.contributor.author VonFange, Ross
dc.date.accessioned 2009-05-19T13:47:39Z
dc.date.available 2009-05-19T13:47:39Z
dc.date.issued 2009-05-19T13:47:39Z
dc.identifier.uri http://hdl.handle.net/2097/1490
dc.description.abstract This thesis presents a novel device for delaying Ethernet traffic in a lab setting. Ethernet is the leading standard for communications between computing devices. With the advent of streaming media such as voice over IP phone service and real-time control systems over Ethernet, applications are being rapidly developed that must meet strict communication reliability and timing constraints. Increasingly, these systems must be examined in real world scenarios before actual hardware deployment or protocol release. This increases the demand for both testing equipment and well trained network engineers. Commercial Ethernet delay testing devices are expensive, hardware specific, and not flexible enough for educational purposes. These short-comings make it necessary to design a robust Field Programmable Gate Array (FPGA) based Ethernet delay device that is up to the rigor of educational and research settings. Our approach is based on the inexpensive, high performance Altera Stratix II GX PCI Express development board which can easily be adapted for different delay scenarios. The system's FPGA hardware was developed in Verilog, an industry standard hardware description language, so users will be able to quickly learn, adapt and operate the system. Software for the system's soft processor was developed in C. The device provides a wide range of packet delay from nearly zero up to over fifty milliseconds, as well as providing an easy to use interface with on-the-fly variable delay adjustment. Theoretical throughput was up to 1Gb/s; skew and jitter measurements were comparable with common network switches. These properties allow the device to provide an easy-to-use, inexpensive method to delay Ethernet traffic in lab settings and the device also creates a starting point for future students and researchers to develop high speed traffic delay testbeds. Future work will include 10Gb/s throughput, additional memory capacity and additional software implemented delay profiles. en
dc.language.iso en_US en
dc.publisher Kansas State University en
dc.subject Ethernet Packet Delay en
dc.title A device for synchronous Ethernet packet delay en
dc.type Thesis en
dc.description.degree Master of Science en
dc.description.level Masters en
dc.description.department Department of Electrical and Computer Engineering en
dc.description.advisor Don M. Gruenbacher en
dc.subject.umi Engineering, Electronics and Electrical (0544) en
dc.date.published 2009 en
dc.date.graduationmonth May en


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