A non-sequential phase detector for low jitter clock recovery applications

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dc.contributor.author Khattoi, Amritraj
dc.date.accessioned 2010-08-10T12:43:35Z
dc.date.available 2010-08-10T12:43:35Z
dc.date.issued 2010-08-10T12:43:35Z
dc.identifier.uri http://hdl.handle.net/2097/4592
dc.description.abstract Clock and data recovery (CDR) circuits form the backbone of high speed receivers. These receivers are used in various applications such as chip to chip interconnects, optical communications and backplane routing. The received data in CDR circuits are potentially noisy and asynchronous, i.e. they are not accompanied by a clock. The CDR circuit has to generate a clock from the data and then retime the data. The CDR circuit that recovers the clock and retimes the data has to remove the jitter that is accumulated during its transport through channels due to inter symbol interference (ISI). There are stringent jitter specifications defined by various communication standards that must be addressed by CDR circuits. These make the design of CDR circuits more difficult for system designers as well the circuit designer. Many parameters have to be taken into consideration while designing a CDR circuit. The problem becomes even more interesting as there are various tradeoffs in the design. As speeds of communications increase, the maximum allowable jitter decreases. Jitter in CDR circuits arises due to a lot of factors and is also dependent on the method used for clock and data recovery. In CDR circuits that use phase locked loops to recover the clock and retime the data, jitter may be caused by the metastability of sequential elements used in phase detectors. Jitter is also caused by the phase noise of the VCO used in the PLL. In CDR circuits that use the delay locked loop to recover the clock and data, jitter may be caused by the metastability of sequential elements in phase detectors as well as the quality of reference clock that is used to re-time the data. Additional effects that can cause jitter in CDR circuits include the use of spread spectrum clocking, delta sigma noise shaping performance, etc. In this thesis a non-sequential linear phase detector has been proposed which does not use any sequential elements to avoid metastability issues in phase detectors. The output jitter in a CDR circuit that uses the proposed phase detector is measured and compared to a Hogge Phase Detector [5]. en_US
dc.language.iso en_US en_US
dc.publisher Kansas State University en
dc.subject Meta-stability en_US
dc.subject Phase Locked Loop en_US
dc.subject Phase Detector en_US
dc.subject Jitter en_US
dc.title A non-sequential phase detector for low jitter clock recovery applications en_US
dc.type Thesis en_US
dc.description.degree Master of Science en_US
dc.description.level Masters en_US
dc.description.department Department of Electrical and Computer Engineering en_US
dc.description.advisor Andrew Rys en_US
dc.subject.umi Engineering, Electronics and Electrical (0544) en_US
dc.date.published 2010 en_US
dc.date.graduationmonth August en_US


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